The present invention relates to an individual selective call receiving apparatus achieving an intermittent receiving operation.
Conventionally, there have been utilized individual selective call receiving apparatuses handling various kinds of signal formats. FIG. 1 shows a representative signal format which is applied to the individual selective call receiving apparatuses in the conventional technology and which has been described in an article "The book of the CCIR Radiopaging Code No. 1" (Radiopaging Code Standards Group; 1986).
In FIG. 1, a transmission code is constituted with a preamble (repeatedly including "1" and "0") and a plurality of batches (first and second batches) following the preamble. The first batch includes a one-word (32 bits) synchronizing code word (SC) and an 8-frame (16 words) selective calling or call code. Accordingly, the respective selective call receiving apparatuses are classified into eight groups such that the receiving apparatuses of a group achieve a receiving operation only for a selective calling code of a frame beforehand assigned thereto.
In order to efficiently receive the code in the format above, the selective call receiving apparatus conducts an intermittent receiving operation.
FIG. 2 shows the configuration of a conventional intermittent receiving apparatus. FIG. 2 includes a bit synchronization unit 701 for detecting a change point of received data represented in the non-return-to-zero (NRZ) code system to generate a clock signal corresponding to the transmission speed, a frame synchronization unit 702 for detecting a synchronizing signal in the received NRZ data to produce a signal associated with an intermediate operation, and an intermediate operation unit 703. In operation, NRZ data is supplied to the bit synchronization unit 701 and the frame synchronization unit 702. The bit synchronization unit 701 then detects a change point of the received data to output the clock associated with the transmission speed to the frame synchronization unit 702.
As a result, the frame synchronization unit 702 detects a frame synchronizing signal in the received NRZ data to output an intermittent operation signal to the intermittent operation unit 703, thereby delivering the signal to the receiver unit through an intermittent operation of the intermittent operation unit 703. Namely, while establishing a synchronization with the transmission signal, the apparatus controls the receiver unit.
On the other hand, during a frame synchronization, each selective call receiving apparatus receives a calling code of a frame (own frame) beforehand assigned thereto and then achieves the collation of the individual calling number (identification or identifier collation).
Subsequently, the conventional method of identifier collation will be described. FIG. 3 is a diagram showing the selective calling code format. A selective calling code includes 32 bits as shown in FIG. 3, namely, bit 1 is an address/message flag, bits 2 to 19 denote a selective calling number, bits 20 and 21 are function bits (specifying a calling tone or sound pattern), bits 22 to 31 are Bose-Chaudhuri-Hocquenghem (31, 32) parity bits, and bit 32 is an even parity.
In the code system of this type, the distance d between codes is six (d=6) and hence a 3-bit error correction is theoretically possible in the collation of the fixed pattern, for example, in the identifier collation. However, ordinarily, a 1-bit or 2-bit error correction is adopted to avoid a risk of an erroneous collation between the identifiers.
Next, the identifier collation method will be specifically described. FIG. 4 shows an example of a conventional ID collating apparatus. In FIG. 4, the configuration includes a number ROM 901 loaded with a selective call number, an BCH generator unit 902 for generating a 32-bit BCH code for the selective call number written in the number ROM 901, a shift register 903 for storing therein the 32-bit code created by the BCH generator 902, a shift register 904 for storing therein received data, a shift register 905 disposed to conduct an identifier collation for the data loaded in the shift register 904, an exclusive OR gate 906 for achieving an exclusive OR between outputs from the shift registers 903 and 905, and a counter 907 for counting signals outputted from the exclusive OR gate 906.
A description will now be given of the operation of the identifier collating apparatus of the prior art. First, a reset signal RES is inputted to the counter 907 to reset the counter 907.
Next, received data (in the NRZ code system) is stored in the shift register 904 in response to a clock CLK1 supplied from the bit synchronization unit 701 shown in FIG. 2.
When the 32-bit data is completedly loaded in the shift register 904, a data transfer takes place to move the data from the shift register 904 to the shift register 905.
Moreover, a code series or sequence produced by the BCH generator 902 depending on the selective call signal loaded in the number ROM 901 is transferred to the shift register. In the situation where the shift registers 903 and 905 are thus loaded with the data, when a clock CLK2 having a higher speed than the clock CLK1 is inputted to the shift registers 903 and 905, the identifier collation is accomplished.
Namely, in response to the clock CLK2, data are respectively read from the shift registers 903 and 905 such that these output items are compared by the exclusive OR gate 906. Resultant signals of the comparison are counted by the counter 907.
In this case, when 32 clocks CLK2 are supplied to the counter 907, the value of the counter 907 is referenced. If a threshold value preset thereto is exceeded by the count value, an identifier collation mismatching is assumed; otherwise, an identifier collation matching results. The operation above is repeatedly carried out for four functions to thereby finish the identifier collation.